Parent Category: 2017 HFE

*By Firas M. Ali Al-Raie*

**Abstract**

High efficiency RF power amplifiers are increasingly employed in modern mobile communication systems to reduce battery size and power supply consumption. Class-F RF power amplifiers offer improved efficiency over conventional class-B power amplifiers by properly controlling the harmonic components of the voltage and current signals at the output terminals of the RF device, while driving it to operate as an ON/OFF switch. To do this task, a suitable load network is to be synthesized in order to present the proper harmonic impedances at the output of the RF power transistor. In this paper, a new load network for class F power amplifiers has been introduced and derived analytically. The proposed network consists of a parallel short circuited λ/8 stub, parallel open circuited λ/8 stub, and a T-section lumped-element transformer. The benefits of this topology include simplicity of design, controllable bandwidth, and harmonic tuning and impedance transformation at the same time.

To confirm the approach of analysis, a 10 W class-F UHF power amplifier circuit has been designed and simulated using a typical Gallium Nitride high electron mobility RF transistor (GaN HEMT) to operate at 500 MHz with the aid of the Advanced Design System (ADS) computer package. The simulated results have indicated that the circuit gives a dc-to-RF efficiency of more than 84 % and a power gain of 11 dB at 500 MHz with an operating bandwidth from 440 to 540 MHz.

**Introduction**

Class F RF power amplifiers are finding widespread applications in modern portable and base station transmitters due to their high-efficiency operation. The idealized operation of the class F RF power amplifier imposes the drain (or collector) voltage to be shaped as a square wave and the drain (or collector) current to be shaped as a half-wave sinusoidal waveform as shown in Fig.1 [1,2]. As seen from this sketch, there is no overlapping between the drain voltage and current waveforms, which means zero dissipated power in the RF transistor and thereby leading to 100% theoretical efficiency. If the RF device is assumed to operate as a switch then the shaping of the drain waveforms can be changed by controlling the harmonic components of the drain voltage and current through the insertion of multiple harmonic resonators in the output matching (or load) network of the power amplifier. These resonators must present open circuit (harmonic peaking) to the odd harmonic components and short circuit (harmonic termination) to the even harmonic components at the device output [3]. Accordingly, the drain to source voltage at the device output contains only odd harmonics while the drain current contains only even harmonics. In other words, the input impedance of the drain network represents an open circuit to the odd harmonics and a short circuit to the even harmonics.

Figure 1 • Idealized waveforms of the drain current and voltage in the class F power amplifier.

The drain voltage of Fig. 1 can be generally described as [4]:

where *V _{dc}*represents the dc voltage at the drain,

*V*is the amplitude of the fundamental component of the drain voltage and

_{d1}*V*is the amplitude of the

_{dn}*n*

^{th}odd harmonic component of the drain voltage.

Similarly, the drain current waveform can be written in the form [4]:

where *I _{dc}*is the dc component of the drain current,

*I*is the amplitude of the fundamental component of the drain current and

_{d1}*I*is the amplitude of the

_{dn}*n*

^{th}even harmonic component of the drain current.

Equations (1) and (2) imply that there is a phase shift of 180˚ between the fundamental components of the drain voltage and current.

Using Fourier series expansion, it can be proved that:

where *V _{dd} *is the drain supply voltage, and

*I*is the maximum or peak drain current of the RF transistor.

_{m}The drain impedance at the fundamental frequency can be defined as:

Substituting equations (4) and (6) in equation (7) yields:

where *R _{opt}*is the optimum load line resistance for the class F mode of operation.

The maximum drain current, *I _{m}*, can be determined from the RF device specifications or from the simulated drain dc characteristics.

In order to avoid distorting the drain current pulse, the drain voltage should not swing below the knee or saturation voltage and therefore equation (8) is modified to be [5]:

where *V _{sat} *is the drain-to-source saturation (or knee) voltage.

The necessary conditions for the input impedance of the load network at the drain of the RF transistor are thus:

The conventional class F switching mode RF power amplifier circuit is presented in Fig. 2 [6]. The input signal is assumed to be a square wave to drive the RF transistor into saturation and cut-off regions consequently. In this circuit the load network consists of a λ/4 transmission line section and a parallel tank circuit tuned at the fundamental frequency. The tank circuit presents high impedance (ideally open circuit) at the fundamental frequency and a short circuit at all other harmonic frequencies. Therefore the transmission line transformer acts ideally as a short circuited λλ/4 stub at all the harmonic frequencies other than the fundamental one. So, it presents a repetitive short circuit at the even harmonics, and a repetitive open circuit at odd harmonics while transforming the load resistance, *R _{L}*, into the optimum class F load line resistance at the fundamental frequency.

Figure 2 • Schematic diagram of the conventional class F RF power amplifier.

A unified method for designing loading networks for class F switching mode power amplifiers using lumped elements was documented [7]. In this technique, the loading networks are synthesized to present infinite impedance at the fundamental frequency and its third harmonic, and low impedance to ground at the second harmonic. A similar approach was reported with new types of loading networks of class F power amplifiers using both lumped and distributed elements [8]. In this approach, explicit-form expressions were derived to evaluate each circuit element in the loading network. However, in these techniques a separate matching network should be added to present the proper load impedance at the fundamental frequency. Besides, these methods are primarily targeted toward narrowband tuned class F power amplifiers.

Another design technique was adopted for both class F and inverse class F power amplifier loading networks using embedded low pass filter sections [9]. In this method, the RF transistor’s lead inductance and output capacitance are considered as part of the loading network. However, the element values of the load network are difficult to be evaluated analytically and require computer optimization. Chebyshev bandpass filters are also used to realize the load networks of class F RF power amplifiers to achieve matching and harmonic tuning at the same time [10]. Unfortunately, the latter technique is somewhat complicated and requires extensive calculations.

**Topology of the Load Network**

The load network of the conventional class F RF power amplifier must present an open circuit at odd harmonic frequencies and a short circuit at even harmonics while presenting the required load line resistance at the fundamental signal frequency. Fig. 3 shows a generalized block diagram of the proposed load network.

Figure 3 • General topology of the load network.

The input impedance of the load network, *Z _{load,}* should satisfy the conditions of

*Z*given in equation (10). The harmonic control circuit, sometimes called the impedance peaking circuit, is synthesized to terminate the second harmonic frequencies and to maximize the odd harmonics of the voltage waveform. The matching circuit, on the other hand, is designed to transform the 50 Ω load resistance into the required optimum resistance for class F operation at the fundamental frequency while giving high impedance at all other harmonic frequencies. The high impedance of the matching circuit is necessary to avoid loading the harmonic control circuit at the harmonic frequencies which may otherwise cause shifting in the frequency response of this circuit. The bandwidth of the matching circuit depends on its quality factor which can be taken as a parameter in the synthesis process.

_{d}In conventional class F power amplifiers, the λ/4 short-circuited transmission line is used to control the harmonics at the drain of the RF transistor. In this work, a new impedance peaking network is introduced as shown in Fig. 4. It consists of two parallel open-circuited and short-circuited λλ/8 stubs having the same characteristic impedance, *Z _{o}*.

Figure 4 • Impedance peaking circuit.

The input impedance of the shorted transmission line can be expressed by [11]:

On the other hand, the input impedance of the open stub is given by [11]:

where *θ* is the electrical length of the two transmission lines.

The input impedance of the peaking network, *Z _{peak}*

_{,}is the parallel combination of

*Z*

_{1}and

*Z*

_{2:}

After some arrangement, equation (13) can be expressed as:

Recalling that:

Thus, equation (14) can be simplified to:

*Z _{peak} *can be expressed as a function of frequency by substituting

*θ*=

*β*ℓ, where

*β*is the phase constant which is given by 2π/λ and ℓ = λ

*/8, where λλ*

_{o}_{o}represents the wavelength at the fundamental frequency component. Based on these facts,

*Z*can be written as:

_{peak}where *f _{o}* is the fundamental frequency of the RF signal.

Equation (17) reveals that the equivalent impedance of the harmonic control network is similar to that of the conventional λλ/4 short-circuited stub but with a multiplication factor of 0.5. This will sharpen the response around the poles and zeros of the impedance function, and give better harmonic peaking and termination characteristics.

In Fig.5, the magnitude of the input impedance of the harmonic peaking circuit is compared with that of the λλ/4 short-circuited stub with a frequency sweep from 0 to 2.6 GHz at a fundamental frequency *f _{o}* of 500 MHz. As shown from this sketch, the impedance response of suggested peaking circuit is narrower around the odd harmonic frequencies. This will give additional reduction of the signals at frequencies around the harmonics of the fundamental frequency.

Figure 5 • Impedance response of the suggested harmonic peaking circuit compared with that of the shorted λ/4 transmission line.

The matching network appearing in Fig. 3 can be synthesized to transform the 50 Ω load impedance into the optimum load-line resistance, *R _{opt,} *at the fundamental frequency. It should also present high impedance to the harmonic frequency components so that not to load the harmonic peaking circuit at these frequencies. The quality factor of the matching circuit can also control the bandwidth of the amplifier circuit. Based on these facts, the T-Section circuit shown in Fig. 6 can be taken to fulfill the desired requirements. The two inductors,

*L*

_{1}and

*L*

_{2}, give high reactive impedance at the harmonic frequencies.

Figure 6 • T-section matching network.

The element values of the T-section matching circuit can be determined after selecting the required Q-factor as follows [12]:

where *f _{o}* is the fundamental frequency of operation,

*A*is a calculated constant, and

*R*= 50 Ω.

_{L}Alternatively, the element values of the matching circuit can be determined graphically using Smith chart with the aid of the constant Q-circle. The topology of the load network will thus be as presented in Fig.7. The T-section matching circuit may however load the harmonic peaking circuit at the odd harmonic frequencies which may cause a slight shift in the impedance peaking points around these frequencies. This frequency shift is mainly dependent on the Q-factor of the matching circuit. The higher the Q, the lower is the shift in the harmonic frequencies.

Figure 7 • Configuration of the proposed load network.

**Design of a 10 W UHF Power Amplifier Circuit**

In order to confirm the validity of the proposed load network, a class-F power amplifier circuit is to be designed at an operating frequency of 500 MHz. In this design the modern gallium nitride (GaN) high electron mobility transistor (HEMT) CGH40010 of Cree, Inc. has been selected. This device operates from a 28 V DC supply and can deliver more than 10 W output RF power up to 4 GHz. This transistor offers also high power gain and broadband operation. The high operating voltage of the GaN HEMT semiconductor technology stems from its relatively high band-gap energy and the corresponding high breakdown electric field. Besides, the high power density offered by the GaN technology allows millimeter size devices with several watts of output power level to be fabricated [13].

Figure 8 • Drain current versus gate voltage for the GaN HEMT transistor.

The transfer characteristic of the CGH40010 GaN HEMT RF power transistor is simulated in Fig. 8 using the SPICE large signal model of this device. This sketch shows that the threshold gate-to-source voltage equals to -2.5 V approximately. This value of *V _{GS}* is taken as the Q-point of the class F mode of operation. In Fig. 9, the drain characteristic of the RF transistor is presented. As shown from Fig. 9, the drain-to-source saturation (or knee) voltage is relatively high and is in the order of 4 V. The maximum allowable drain current for this device is specified by the manufacturer’s datasheet to be 1.5 A. Hence, the optimum load line drain resistance at the fundamental frequency,

*R*, is calculated from equation (9) to be 40 Ω.

_{opt}Figure 9 • Drain current versus drain-to-source voltage.

To design the load network, the Q-factor of the matching circuit should first be determined. It actually depends on the desired bandwidth of power amplifier circuit and can be estimated from:

Since the operating frequency of the circuit, *f _{o}*, is 500 MHz, therefore the Q-factor equals to 5 for a desired bandwidth,

*BW*, of 100 MHz. Practically, the Q-factor should be selected to be less than the calculated value in order to account for the parasitic elements of the circuit which may decrease the overall bandwidth.

Figure 10 • Impedance response of the load network with different quality factors.

The circuit elements of the matching network are calculated from equations (18-21) to transform the 50 Ω impedance into 40 Ω (*R _{opt}*) at the fundamental frequency for the given Q-factor. For a value of Q = 2, the element values are

*L*

_{1}= 25 nH,

*L*

_{2}= 27 nH, and

*C*= 6 pF. In Fig. 10, the impedance response of the load network in Fig. 7 is presented for two values of quality factor. Although the two circuits present the same impedance (40 Ω) at the fundamental frequency, there is a slight shift in the response at the third harmonic frequency (1.5 GHz). When Q = 5, the load network presents a third harmonic impedance of 556 Ω, while it is reduced to 216 Ω when the quality factor is 2. However, the load network gives wider bandwidth when Q = 2.

The block diagram of the class-F RF power amplifier is shown in Fig. 11. The input matching network is designed to match the large signal input impedance at the gate terminal of the HEMT transistor with the 50 Ω system impedance. The stability network is a resistive (lossy) circuit used to prevent any tendency to oscillation and to increase the stability factor of the amplifier [14].

Figure 11 • Block diagram of the RF power amplifier.

In order to design the input matching network, the input impedance of the RF power device should first be evaluated over the desired bandwidth with the load and stability networks inserted in the amplifier circuit. Fig. 12 presents a schematic diagram of the power amplifier circuit without the input matching network. The transmission line sections are implemented as two microstrip lines using FR-4 substrate with a dielectric constant of 4.5 and a board thickness of 1.6 mm. The drain supply voltage is delivered to the HEMT transistor through the short-circuited stub of the load network, which is in turn connected to RF ground via a 470 pF bypass capacitor. The HEMT transistor is biased at the threshold gate-to-source voltage to place the RF device at the edge of the cut-off region. Resistor *R*_{1} and inductor *L*_{3} represent the stability network to ensure stabilized amplifier operation over the desired band. The values of *R*_{1} and *L*_{3} have been optimized using ADS simulation capabilities. The circuit is analyzed using the harmonic-balance algorithm to evaluate the input impedance at the gate of the transistor over the frequency band from 440 MHz to 540 MHz with the input RF power set to 1 W.

Figure 12 • Circuit schematic of the class F power amplifier without the input matching network.

The input impedance at the gate terminal of the HEMT transistor is presented in Fig. 13 across the frequency band of interest. This sketch indicates that the gate impedance is capacitive with a value of *Z _{g}* = 11-j46 Ω approximately at 500 MHz. An input matching network is hence needed to transform the gate impedance into 50 Ω in order to minimize the input voltage standing wave ratio (VSWR) of the overall power amplifier circuit. With the aid of the Smith chart, a matching circuit consisting of a series inductor with a value of 23 nH and a parallel capacitor of 8.2 pF is synthesized for this purpose. The schematic diagram of the overall power amplifier circuit is presented in Fig. 14.

Figure 13 • Simulated gate impedance versus frequency.

Figure 14 • Schematic diagram of the designed class F power amplifier

**Simulation Results**

The designed power amplifier circuit of Fig. 14 has been simulated with the aid of the harmonic balance simulator of the ADS software package. Fig. 15 presents the drain voltage waveform of the HEMT transistor, while Fig. 16 shows its drain current waveform at 500 MHz with an input power level of 1 W. The simulated drain voltage waveform looks like a semi-square wave when compared with the ideal waveform of Fig. 1. This waveform is shaped by the response of the load network in addition to the nonlinear output capacitance and lead inductance of the RF power device. The drain current waveform of Fig. 16 is an approximation of the half-wave sinusoidal pulses and seems to be out of phase with the drain voltage waveform with minimum overlapping. This non-overlapping behavior reduces the power dissipation in the drain of the HEMT transistor and increases power amplifier’s efficiency.

Figure 15 • Simulated drain voltage waveform at 500 MHz.

Figure 16 • Simulated drain current waveform at 500 MHz.

Figure 17 • Simulated output voltage signal at 500 MHz.

In Fig. 17, the output voltage waveform of the power amplifier circuit is sketched. The sinusoidal nature of this waveform is referred to the low-pass filtering effect of the output matching network in minimizing the amplitudes of the harmonic components.

In Fig. 18, the output power is sketched against input power level in dBm with a simulation frequency of 500 MHz. It is shown that the amplifier delivers more than +40 dBm (10 W) at input power level of 30 dBm (1 W). It can be seen from this sketch that the RF device goes deeply into saturation at this power level. The power gain of the amplifier circuit is presented in Fig. 19, being about 11 dB at input power level of 30 dBm. The 1-dB gain compression point occurs at an input power of 15 dBm with the power gain falling rapidly after this point.

Figure 18 • Output power versus input power.

The drain efficiency of the power amplifier is sketched in Fig. 20 together with the power-added efficiency (PAE). It is shown that the circuit possesses a drain efficiency of 84.8 % and a power added efficiency of 78.2 % at input power level of 1 W. The drain efficiency, also known as the DC-to-RF efficiency, is calculated from:

where *P _{out} *is the output RF power, and

*P*is the dc delivered power given by:

_{dc}*V _{dd}* represents the drain supply voltage and

*I*is the dc component of the drain current.

_{dc}On the other hand, the power added efficiency of the circuit is calculated from:

Figure 19 • Simulated power gain versus input power.

Figure 20 • Efficiency versus input power.

The circuit has then been simulated over a frequency band from 440 MHz to 540 MHz with the input power maintained at 1 W. Fig. 21 presents the power gain of the amplifier versus frequency. It is shown that the power gain is about 10±1 dB over the entire band. In Fig. 22, the output power is sketched with frequency, while Fig. 23 displays the drain efficiency and power added efficiency of the circuit. The power amplifier circuit gives a dc to RF efficiency of more than 80 %, and a power-added efficiency of more than 75 % all over the band. Finally, the input return loss is displayed in Fig. 24 showing an acceptable match over the frequency band of interest.

Figure 21 • Power gain versus frequency.

Figure 22 • Output power versus frequency.

Figure 23 • Efficiency versus frequency.

Figure 24 • Input return loss versus frequency

**Conclusion**

A load network topology for class F switching mode RF power amplifiers has been proposed and analyzed. The main features of the network are its simplicity of construction, controllable bandwidth, and predictable behavior. The proposed network has been verified through a design process of a 10 W class F power amplifier operating within the frequency band 440-540 MHz using a modern HEMT RF power transistor. The simulation results show that a drain efficiency of more than 84 % has been obtained at 500 MHz with a power gain of 11 dB at the nominated output power level. Although this network consists of both lumped and distributed elements, it can be modified to be constructed solely of distributed elements (microstrip lines) by replacing the T-section matching circuit with an equivalent transmission-line network. This may increase the operating frequency of the circuit into the giga-hertz range. It has been verified also that flat broadband power amplifier response can be obtained with careful design using the proposed network topology.

**References**

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F. H. Raab, “An Introduction to Class-F Power Amplifiers”, *RF Design, *Vol. 19, No. 5, pp. 79-84, 1996.

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**About the Author**

Firas M. Ali Al-Raie is a Lecturer in the Department of Electrical Engineering at the University of Technology, Baghdad, Iraq. He obtained his BSc Degree in Electrical Engineering from the University of Baghdad, College of Engineering in 1994 (Ranked 1). He obtained his MSc Degree in Electrical Engineering in the field of Electronics and Communication from the University of Baghdad in 1997. E-mail: firas@ieee.org, 30204@uotechnology.edu.iq.

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