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A Non-Linear Analysis of the Saturated MOSFET

Parent Category: 2018 HFE

By Dr. Alfred Grayzel

Abstract: The maximum power and the maximum efficiency at the maximum power have been derived for the MOSFET; when the MOSFET is in saturation over the entire cycle, using the square law theory. Results are presented for the following three cases: the gate voltage is a sinusoid, a half sinusoid and a square wave. Results using the square law theory and bulk-charge theory for analysis of the MOSFET are compared.

Introduction

When a MOSFET is saturated, the drain current is not a function of the drain voltage; it is only a function of the gate voltage. The load impedance thus has no effect on the drain current. The MOSFET amplifier can therefore be easily analyzed if the MOSFET is in saturation over the complete cycle. In this paper the n-type MOSFET amplifier is analyzed utilizing the non-linear equations that describe the physics of the MOSFET, for the case where the MOSFET is in saturation for the entire cycle. A similar analysis is given in [1] for the JFET. For a given input excitation the drain current can be calculated as a function of time and the Fourier components can be calculated. The output power and the efficiency can then be calculated for a given load resistance and DC bias voltage. For the n-type MOSFET the maximum power and the maximum efficiency at the maximum power are presented for a given load resistance, when the gate voltage is a sinusoid, a half sinusoid and a square wave. The maximum power and efficiency are compared for these three excitations.

The MOSFET: Sinusoidal Input Voltage Excitation -- Square Law Theory

There are two theories for obtaining a relationship for the drain current as a function of the gate voltage, when the MOSFET is in saturation; the square law theory and the bulk-charge theory. In the following analysis the square law theory will be used as it is simpler and gives good insight into the performance of the MOSFET. The results will then be compared to the results using the bulk-charge theory. Idsat is given by Eq. 1 when using the square law theory [2].

Idsat= (Zµ’nC0/2L )(Vg - VT )2(1)

where Idsat is the drain current when the MOSFET is in saturation, µ’n is the average mobility of the inversion layer carriers, C0 is the oxide capacitance, Z is the width of the channel and L is its length.

The first case considered is the sinusoidal case where Vg is given by Eq. 2.

Vg = (Vgmax + VT)/2 + [ (Vgmax - VT )/2] Cos(ωt)(2)

Vg has a maximum value of Vgmax and a minimum value of VT. Substituting Eq. 2 into Eq. 1 yields:

Idsat = (Zµ’nC0/2L)[(Vgmax - VT) (1 + Cos(ωt) ) /2]2(3)

Idss, the maximum saturated drain current, is given by Eq. 1 with Vg set equal to Vgmax.

Idss = (Zµ’nC0/2L)(Vgmax - VT)2(4)

Dividing Eq. 3 by Eq. 4 yields Eq. 5.

Idsat/Idss  =[ (1 + Cos(ωt) ) /2]2

              = 3/8 + 1/2 Cos(ωt) +1/8 Cos(2 ωt)(5)

Eq. 5 yields a DC current I0Idss, equal to (3/8)Idss and a current at the fundamental frequency I1Idss equal to Idss/2. The DC power is given by Eq. 6.

P0 =I0IdssV0 = (3/8)IdssV0(6)

where V0 is the DC bias voltage. The output power at the fundamental frequency P1, is given by Eq. 7.

P1 = (IdssI1)2RL/2(7)

1806 MOSFET fg1

Figure 1 • Idsat/Idss as a function of theta computed using Eq. 5 and twelve cases analyzed by computer program.

The drain current is not a function of the drain voltage when the MOSFET is in saturation; it is only a function of the gate voltage and it therefore, is not affected by the load impedance. Since only the fundamental frequency is desired at the output, the load impedance should present a short-circuit at all of the harmonic frequencies. Only voltage at the fundamental frequency will then appear across the drain and across the load resistor. Since for a MOSFET, Vdsat is equal to (Vg – VT) [2], the constraint that the MOSFET is in saturation over the entire cycle and the harmonics are short circuited to ground requires that the amplitude of the fundamental frequency can be no greater than V0 – (Vgmax - VT). The minimum value of the drain voltage is then equal to (Vgmax-VT); which is the saturation voltage when the gate voltage is equal to Vgmax and the maximum value is equal to 2V0 – (Vgmax -VT). Since the drain current flowing through the load resistor is sinusoidal and has a value I1Idss,the load resistance is given by Eq. 8.

RL = (V0 - (Vgmax - VT)|) /(I1Idss) (8)

Solving Eq. 8 for V0 yields Eq. 9.

V0 = (I1Idss) RL + (Vgmax - VT)(9)

P1 = (I1Idss)2RL/2 = (I1Idss) (V0 - (Vgmax - VT))/2 (10)

The output power for the sinusoidal case is thus given by Eq. 11.

P1 = .25( Idss) (V0 - (Vgmax - VT))

(11)

The efficiency is given by Eq. 12:

Eff =P1 /P0 = EFF0(V0 – (Vgmax - VT))/V0=  (I1 /2I0 )(V0 – (Vgmax - VT))/V0 (12)

where EFF0 is equal to I1/2I0, which is equal to 2/3 for the sinusoidal case.

Computer Analysis

To compare the accuracy of the square law theory with that of the bulk–charge theory a simple program was written where the following instructions were performed.

1.
Read from an input file Vgmax, X0, NA, Z/L and µ’n where Vgmax  is the maximum value of the gate voltage, X0 is the thickness of the oxide layer, NA is the doping concentration of the p-type semiconductor, Z/L is the ratio of the width to the length of the channel and µ’n is the effective mobility in the channel.

2.
Using Eq. 13 find Vdsat; the drain voltage at pinchoff when the gate voltage Vg is equal to Vgmax. The equations and definitions for the functions appearing in Eq. 13 are given in [3].

Vdsat = Vg – VT – VW{ [(Vg – VT)/2фF + (1+ VW/4фF)2 ]1/2 - (1+ VW/4фF)}(13)

3. Using Eq. 14 find Idss by setting the gate voltage Vg equal to Vgmax  [4].

Idsat = (Z/L)( µ’n)C0{ (Vg – VT)Vdsat- Vdsat2/2- 4VWфF/3[(1+ Vdsat/2фF)3/2 – (1+ 3Vdsat/4фF)]}(14)

4. Define 1,440 points by incrementing theta from 0 to 360 degrees in increments of 360/1440 degrees.

5.
At each of these points calculate Vg given by Eq. 2 and using these values of Vg, calculate Idsat at these 1440 points using Eq. 14.

6. Calculate Idsat/Idss at these 1440 points and plot Idsat/Idss in Figure 1.

7. Calculate the Fourier Coefficients I0 and I1, using Simpsons rule.

8. Calculate EFF0 = I1/2I0.

The results are shown for twelve cases in Table 1. The values of EFF0 in Table are within 0.5% of the value calculated using Eq. 12. Figure 1 shows plots of Ids/Idss as a function of THETA for all twelve cases. Idsat/Idss calculated using Eq. 5 is also plotted in Figure 1. The curves are so close to one another that they appear as a thickened curve. Thus, the square law theory is in very good agreement with the bulk-charge theory for the calculation of Idsat /Idss. The two theories differ however, in the values of Idss and Vdsat [5].

1806 MOSFET tb1

Table 1.

For a given value of RL increasing V0 does not increase the output power since the drain current is saturated. It will however increase the D.C. power and hence reduce the efficiency. Decreasing V0 on the other hand will decrease the output power since for part of the cycle the drain current will be less than the saturation current. For a given value of RL, Eqs. 9, 10 and 12 give the maximum power and the efficiency at the maximum power. The power and efficiency will be increased by increasing RL and therefore the load resistance should be as large as possible without exceeding the maximum allowed drain voltage.

The MOSFET: The Half Sinusoidal Input Voltage Excitation

The second case to be considered is the half sinusoidal case where for half of the cycle Vg is a sinusoid with a maximum value of Vgmax and a minimum of VT and for the other half of the cycle Vg is equal to VT. Vg is given by Eq. 15

Vg  =VT  + (Vgmax - VT )Cos(ωt)-90o<ωt< 90o

Vg = VTotherwise (15)

Substituting Vg into Eq.1 and dividing by Eq. 4 yields

Idsat /Idss= Cos2(ωt)-90o<ωt< 90o

Idsat / Idss= 0otherwise(16)

Idsat/Idss is then equal to the product of Cos2(ωt) and a square wave of unit magnitude centered at ωt=0. Using the Fourier expansion of the square wave and the trigonometric identity for Cos2 (ωt), Idsat/Idss can be written as:

Idsat /Idss=.5(1+Cos(2ωt))(.5 + (2/π)(Cos(ωt) – Cos(3ωt)/3 + Cos(5ωt)/5...)(17)

Multiplying the two factors and using the trigonometric identity for the product of two cosines yields Eq. 18.

Idsat / Idss= .25 + (4/3π)Cos(ωt) + (.25) Cos(2ωt) + (4/17π)Cos(3ωt) + …(18)

It can be seen from Eq. 18 that I1 is equal to 4/3π and I0 is equal to .25. The DC power is given by Eq. 19;

P0 = I0 Idss V0 =IdssV0/4 .(19)

The drain current is not a function of the drain voltage when the MOSFET is in saturation; it is only a function of the gate voltage and It therefore is not affected by the load impedance. Since only the fundamental frequency is desired at the output the load impedance should present a short-circuit at all of the harmonic frequencies. Only voltage at the fundamental frequency will then appear across the drain and the load resistor. For a given value of V0 the load resistance RL is given by Eq. 8. The output power is given by Eq. 10, which for I1 = 4/3π is given by Eq. 20.

P1= Idss (4/3π) (V0 - (Vgmax - VT )/2  = Idss(.212) (V0 - (Vgmax - VT ))(20)

The efficiency equal to P1/P0 where I1 = 4/3π and I0 = .25 is given by Eq. 21.

Eff  =EFF0(V0 - (Vgmax - VT)/V0 =  (.849)( V0 - (Vgmax - VT))/V0(21)

Comparison of Eqs. 20 and 21 with Eqs. 11 and 12 shows that the half sine wave input excitation will give greater efficiency than the sine wave excitation but less output power.

The MOSFET: Square Wave Input Voltage Excitation

The third case to be considered is a square wave excitation, where for half of the cycle Vg is equal to Vgmax and for the other half of the cycle Vg is equal to VT. Vg is given by Eq. 22.

Vg  = Vgmax-90o<ωt< 90o

Vg = VTotherwise(22)

Substituting Vg into Eq.1 and dividing by Eq. 4 yields:

Idsat /Idss= 1-90o<ωt< 90o

Idsat /Idss= 0otherwise(23)

Idsat /Idss is a square wave of unity magnitude, centered  at ωt equal to zero, whose Fourier series is given by Eq. 24.

Idsat / Idss= (.5 + (2/π)Cos(ωt) – (2/3π)Cos(3ωt) + (2/5π) Cos(5ωt))   ……… )(24)

It can be seen from Eq. 24 that I1 is equal to 2/π and I0 is equal to .5.

The drain current is not a function of the drain voltage when the MOSFET is in saturation; it is only a function of the gate voltage and It therefore, is not affected by the load impedance. Since only the fundamental frequency is desired at the output the load impedance should present a short-circuit at all of the harmonic frequencies. Only voltage at the fundamental frequency will then appear across the load resistor. For a given value of V0 the load resistance RL is given by Eq. 8.The output power is given by Eq. 10, which for I1 = 4/3π is given by Eq. 25.

P1= Idss (2/π) (V0 - (Vgmax - VT)/2  =(.318) Idss (V0 - (Vgmax - VT))(25)

The efficiency equal to P1/P0 is given by Eq. 26 for I1 = 2/π and I0 = .5.

Eff  = [I1 /(2 I0)][(V0 - (Vgmax - VT)/V0] =  (.636)( V0 - (Vgmax - VT))/V0(26)

Comparison of the values of EFF0 and P1 for the sine wave, the half sine wave and square wave cases show that the square wave input excitation gives the greatest output power while the half sine wave input excitation gives the greatest efficiency.

Conclusion

The maximum power and the maximum efficiency at the maximum power have been derived for the MOSFET amplifier when the MOSFET is in saturation over the entire cycle. Three cases were considered: the gate voltage is a sinusoid, a half sinusoid and a square wave. The MOSFET was analyzed using the square law theory. The results were compared to the results using the bulk-charge theory and it was found that the square law theory is in very good agreement with the bulk-charge theory for Idsat/Idss. The two theories differ in the value of Idss and in the value of Vdsat. Equations are given for the maximum output power and the efficiency, load resistance and DC voltage and at the maximum output power.

About the Author

Dr. Alfred Grayzel is a consultant to Planar Monolithic Industries, Inc.

Acknowledgement

The author wishes to acknowledge the support given by Dr. Ashok Gorwara, CEO of Planar Monolithics Industries, Inc. (PMI), and the support provided by the staff of PMI.

References

[1] A. I. Grayzel, “Analyze RF JFETS for Large-Signal Behavior,” Microwaves&RF, February 2017, pp 50-55. (Available at:pmi-rf.com/tech-papers.htm)

[2] R. F. Pierret, Semiconductor Device Fundamentals, Pearson Education Noida, India, 2006, page 623.

[3] Ibid pp. 573, 579, 587, 617, 626.

[4] Ibid page 626.

[5] Ibid page 627

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