Tuesday, May 28, 2024

Chip, Package, and Board Beamforming Solutions

Parent Category: 2022 HFE

by Cadence AWR


RF front-end architectures grow more complex with each generation of communication systems. To accommodate these architectures, more densification and miniaturization is taking place with electronic systems implemented through innovations in system-in-package (SiP) design.

5G data rates exceeding 1GB/s will be supported by the available bandwidth in the millimeter-wave (mmWave) spectrum and use of beam steering phased array antennas and multiple communication chains, which can range from eight to 64 elements in a typical system. A reference design (shown in Figure 1) has been developed to demonstrate how Cadence® software tools, inclusive of the AWR Design Environment® platform, support the development of such a system, from the 5G antenna array on a PCB through the package-on-package design and complementary metal-oxide semiconductor (CMOS) receiver IC.

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Figure 1.

The reference design was developed with a full range of Cadence solutions, including:

  • Cadence AWR® Visual System Simulator™ (VSS) system design software for budget analysis and component specification, phased array configuration, and simulation of digital modulation measurements such as adjacent channel power ratio (ACPR), error-vector magnitude (EVM), and bit-error rate (BER).
  • Cadence Virtuoso® RF Solution and Spectre® RF Option for design entry and simulation of the 45nm CMOS RFIC eight-channel receiver chip
  • Cadence EMX® Planar 3D Solver for analysis of on-chip passives and interconnects
  • Cadence AWR AXIEM® 3D planar electromagnetic (EM) simulator for analysis of PCB feed structure and eight-element (4x2) antenna array
  • Cadence Allegro® PCB Designer for physical layout design
  • Cadence AWR Microwave Office® circuit design software for III-V and off-silicon circuit design

System Budget Analysis

System designs often start with budget analysis used to define the RF link, calculate the cascaded performance of the RF link, and determine individual component specifications. The reference design began with back-of-the-envelope approximations taken from published literature, including likely component block performance based on historical results for the target IC process, system requirements (data rates and coverage range), channel losses, allowable transmitter effective isotropic radiated power (EIRP), and receiver sensitivity (Figure 2).

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Figure 2.

In this case, the thermal noise floor for a 400MHz bandwidth is calculated to be -85dBm, assuming the receiver has a cascaded noise figure (NF) of 6dB that increases the noise floor to -79dBm, which requires a signal strength of at least -75dBm (per antenna element) to achieve a minimum signal-to-noise ratio (SNR) of 4dB. To obtain that received power level (-75dBm), working back towards the transmitter through a line-of-sight (LOS) path loss of 135dB requires an EIRP of 60dBm, which translates into an output power of 33dBm (2W) from the base station PA for an antenna with 27dB of gain.

AWR VSS software was used to characterize the receiver chain with behavioral models, performing budget analysis to obtain the overall cascaded figures of merit and spur heritage to examine the impact of nonlinearities on generating unwanted tones in the system. These analyses helped guide early design decisions such as P1dB and IP3 considerations to reduce unwanted harmonics from device nonlinearities, as well as filtering to mitigate interference. Furthermore, AWR VSS software can perform time-domain analyses from the same schematic to investigate BER, IQ constellation plots, and spectral regrowth, as shown in Figure 3.

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Figure 3.

RFIC Receiver Design and Analysis

After obtaining the desired channel link budget response, attention can be turned to developing the individual RF front-end blocks at the circuit (transistor) level with layout and construction of the eight-channel receiver in both AWR VSS software and the Virtuoso RF Solution (Figure 4). The RFIC was designed in Virtuoso RF Solution using a generic process design kit (PDK) based on 45nm CMOS technology and simulated using the harmonic balance (HB) engine available in Spectre RF Option. The EMX Planar 3D Solver was used to extract the broadband response of the on-chip passive components and interconnects.

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Figure 4.

The post-layout Spectre RF Option simulation results were then used to create data files (S-parameter, phase noise mask, spur table, or am/am-am/pm) in AWR VSS software to provide a greater level of detail defining the behavior of the various blocks, thereby increasing the accuracy of the simulation. The schematic, layout, and post-layout simulation results for the individual component blocks are displayed in Table 1.

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Table 1.

Packaging and PCB Development

The next phase of the design focuses on the heterogeneous integration of the RFIC into the packages and development of the PCB with an embedded 2x4 patch antenna array. To implement the packaging, the RFIC design (parasitic-aware schematic) was exported to a SiP as a simple footprint for place and route operations using the schematic-to-SiP layout feature from the RF module pull-down menu in the Virtuoso Schematic Editor. The next step was to bind this footprint to the original IC schematic symbol or sub-circuit. This is the same symbol that the IC designer has been using in the top-level IC simulations. The Virtuoso System Design Platform provides an intelligent mapping mechanism to create a 1:1 map between the footprint terminals and the IC symbol terminals (Figure 5).

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Figure 5.

Package-aware RFIC simulation can then be performed based on EM extraction of critical nets from the package design layout. Specific to this design, the Clarity 3D Solver can be used to extract the interconnects between the individual RFIC receiver channels through the package routing to each element of the patch antenna array on the PCB. To focus strictly on the PCB feed and antenna array response, the board layout was imported into the AWR Design Environment platform through the IPC-2581 file format for EM analysis with the AWR AXIEM analysis. In addition to S-parameter extraction, AWR AXIEM analysis can provide surface currents and radiation plots of the individual patch antennas or the entire array (Figure 6).

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Figure 6.

Physical Array Configuration

In addition to EM analysis of the initial array, the designers used the phased array generator wizard in AWR VSS software to rapidly configure the physical array, assign antenna radiation patterns derived from AWR AXIEM analysis for the individual patch antennas, and model mutual coupling and edge/corner behavior. The wizard also allows designers to specify link and feed performance, incorporate gain tapering to reduce antenna side lobes, and investigate the impact of element failures on the overall array performance. It provides real-time visualization of far-field radiation patterns from all these user-specified parameters and then automatically generates either a system or circuit-based network in AWR Microwave Office software for further development and EM/circuit analysis of the complete array, as shown in Figure 7. The resulting array can also be incorporated into the receiver design link.

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Figure 7.


Next-generation communication systems targeting 5G/6G functionality will provide massive connectivity to the internet with extreme capacity, coverage, reliability, and ultra-low latency, enabling a wide range of new services and business opportunities. The anticipated performance will be made possible through a range of innovative technologies, implemented though complex RF front-end architectures and highly integrated multi-fabric electronics. RF to mmWave design and multi-fabric design and manufacturing software will be critical to the development of these technologies.

This article has presented challenges and solutions for engineers designing complex RF front-end architectures implemented through next-generation SiPs.

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